Suck it, Verilog
May 28th, 2004
I should mention that the thing that we were programming in Verilog (see the previous post), actually ended up working perfectly. Assfacey Verilog notwithstanding. It was close, though.
You see, I had lost all faith in the academic system by this point and had resolved to skip every class and instead play ping-pong until my arms turned blue and purple and black and then brown and ultimately greenish. So after skipping my first two classes, it occured to me to check on my partner and see if he was working on the project.
He was, and, justifiably, he was a bit miffed (What?! I worked later than you, and gave you a bunch of stuff if you'd check your email). But I can't stop the ping-pong urge, man. It's ping-pong. I mean... wap, wap, wap... it's cool.
So at that point I could no longer play ping-pong and instead started schooling Verilog on not being such an ugly whore. My partner and I got the thing running a little bit later. And half-way into the class during which it was due, we finally squashed every bug. Score! Our single-cycle processor was complete and functional, and we's gots'd full credit.
Because, you know, the only reason to do anything is for a credit fix. *Taps arm* *Shivers* *Drops to knees* *Prays to god of academic institutions*
Note: A single-cycle processor is not a processor that runs for a single cycle. That would be hella lame. It means that one instruction takes one cycle and performs no other instructions simultaneously (i.e. CPI = 1).
So now we've graduated to working on a pipelined processor (Hah! Did you think I was gonna say we've graduated college?! No way! Not ever!). And it's going pretty smoothly, but it always goes smoothly until you try to run it, so that's not exactly saying a whole lot. But we're confident, and Verilog is our bitch.
So, as the title indicates: Suck it, Verilog.
