May 14th, 2004

This was a random white pole that was held up by a circular metal base with the sguiggly lines in the picture. It was at the local airforcebasepark.

I fucking hate Verilog!

For those who don't know, Verilog is a programming language used for designing processors and circuit logic type stuff. Processors and circuit logic type stuff are cool, Verilog is not.

Its documentation is somewhere between shitty and nonexistent and it's no good at communicating. If it were in a relationship, it would already have a big shoe mark on its forehead. Its significant other would tell everyone they know how Verilog is such a neglecting bastard with whom it would be a grave mistake to hang out. Verilog will blithely whistle while it pisses as you accidentally walk off a cliff... to your certain doom. And Verilog wouldn't even stop fucking whistling.

Anyway, because Google indexes things and is a pretty decent troubleshooting resource, I will say a few words in the hope that my advice will be indexed by the powers that be.

The first thing I wanna say: if you get lots of z's. It's because you didn't hook it up right. But you probably got that far already. Here's an example of a situation where you would get z's (I probably shouldn't be using apostrophes, but ass). Say you've got a testbench file that you're testing some modules with, you make some regs so that you can control the inputs and then you have some instances of the modules that you want to test.

Now, say, it's really late and you aren't thinking straight. You make some wires because you want to connect the registers to the modules, but you've forgotten that you can directly put the register in the module declaration without using wires. So they aren't actually connected (you just connected the wire to the module, but not the register). Then you monitor the wires. You see... wait for it... a bunch of enigmatic z's.

So there you have it, that's your problem. Z's mean that it's not hooked up to anything, it's just sitting there (this is why I say Verilog can't communicate, I mean, isn't that important?). X's mean it's hooked up, but hasn't picked a value yet, or can't decide or something. I might be making this all up. And because I think Google would like it, I'm going to say a few words now... Verilog, um... zee, eh... zzz, uh, Verilog, again. And troubleshooting z's and monitor and burgeoning bosoms (wait, how'd that get in there?).

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